Simultaneous Ptl Buuer Insertion and Sizing for Minimizing Elmore Delay

  • Elmore DelayI-Min Liuy Tai-Hung Liuy Hai Zhouz Adnan AzizyyElectrical
  • Published 1998
Minimizing Elmore Delay I-Min Liuy Tai-Hung Liuy Hai Zhouz Adnan Azizy yElectrical and Computer Engineering zComputer Sciences The University of Texas The University of Texas Austin TX Austin TX Abstract For many digital designs, implementation in pass transistor logic (PTL) has been shown to be superior in terms of area, timing, and power characteristics… (More)