Simultaneous Peak Temperature and Average Power Minimization during Behavioral Synthesis

@article{Krishnan2009SimultaneousPT,
  title={Simultaneous Peak Temperature and Average Power Minimization during Behavioral Synthesis},
  author={Vyas Krishnan and Srinivas Katkoori},
  journal={2009 22nd International Conference on VLSI Design},
  year={2009},
  pages={419-424}
}
With continuous CMOS scaling and increasing operating frequencies, power and thermal concerns have become critical design issues in current and future high-performance integrated circuits. Elevated chip temperatures adversely impact circuit performance and reliability. On-chip thermal gradients can lead to unpredictable clock skew variations and timing failures. Chip temperatures are influenced by design decisions at the behavioral and physical-synthesis levels. Existing low-power design… CONTINUE READING