Modular verification approaches have recently gained attention to enable cost efficient handling of changes in safety critical embedded systems. First results in this field are based on formal languages and iterative change processes to analyze the neighboring design elements of the change and thereby determine the effects of the change and possible inconsistencies. The alternative, being mostly applied in practice, is the complete re-verification of modules or even the whole product. In this paper we present simulation results comparing the effectiveness of both approaches by analyzing their effort of re-validation to regain a consistent set of requirements and implementations. As modular re-verification strategies execute only the needed analyzes, the effort progresses linearly with the number of necessary changes within the system. Consequently, we find that for a small number of changes this approach presents a huge saving in contrast to the commonly used approach of complete re-verification. Surprisingly, the critical portion of changes over the system size at which both approaches perform equally well is relatively small.