Simulations of sub-100nm strained Si MOSFETs with high-k gate stacks


Scaling of Si MOSFETs beyond the 90 nm technology node requires performance boosters in order to sustain the annual increase of intrinsic speed of high-performance (2003). One potential solution is transport enhanced FETs using strained Si channels. High-k dielectrics required to reduce the gate leakage current for equivalent oxide thickness (EOT) are expected to replace SiO/sub 2/ around the 65 nm node in order to enable further scaling. However, achieving high-quality high-k dielectrics on top of Si is problematic (Wilk et al., 2001). Aside from these technological issues, a fundamental drawback of MOSFETs with high-k dielectrics is the mobility degradation due to strong soft optical (SO) phonon scattering (Fischetti et al., 2001). In this work we study the impact of interface roughness and soft optical phonon scattering on the performance of conventional and strained Si n-MOSFETs with high-k dielectrics using a self-consistent ensemble Monte Carlo (EMC) device simulator. The simulated device structures are illustrated.

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@article{Yang2004SimulationsOS, title={Simulations of sub-100nm strained Si MOSFETs with high-k gate stacks}, author={Liguo Yang and J. R. Watling and F. Adam-Lema and A. Asenov and J. R. Barker}, journal={2004 Abstracts 10th International Workshop on Computational Electronics}, year={2004}, pages={30-31} }