Simulation techniques for noise-analysis in the PLL design process

@article{Anders2006SimulationTF,
  title={Simulation techniques for noise-analysis in the PLL design process},
  author={Jens Anders and Wolfgang Mathis},
  journal={2006 IEEE International Symposium on Circuits and Systems},
  year={2006},
  pages={4 pp.-}
}
The phase-locked loop (PLL) has become one of the most commonly used circuits in electrical engineering nowadays. Therefore, there is a great need for both a solid mathematical theory, especially in the presence of noise, and practical design rules that help the PLL designer to improve the circuit performance. Although numerous papers have been published on… CONTINUE READING