• Corpus ID: 1911635

Simulation and Analysis of 2:1 Multiplexer Circuits at

  title={Simulation and Analysis of 2:1 Multiplexer Circuits at},
  author={Ila Gupta and Neha Arora and B. Prasad Singh},
A multiplexer, sometimes referred to as a "MUX", is a device that selects between a numbers of input signals. It is a unidirectional device and used in any application in which data must be switched from multiple sources to a destination. This paper represents the simulation of different 2:1 MUX configurations and their comparative analysis on different parameters such as Power Supply Voltage, Operating Frequency, Temperature, Load Capacitance and Area Efficiency etc. All the simulations have… 

Analysis of Various DCVSL Structures and Implementation of Full Adder with Them

A detailed comparison of all the DCVSL structures are provided including the implementation of Full Adder circuit with the help of those DCvSL structures, which includes Static DCV SL, Dynamic DCVsl and Modified DCV Sl, to achieve speeds and high drivability.

Design of area and power aware reduced Complexity Wallace Tree multiplier

The work has been done to reduce the area by using energy efficient CMOS Full Adder to implement the high-speed multiplier, Wallace tree multiplier, which will have fewer adders than Standard Wallace multiplier (SWM).

Performance analysis of reduced complexity Wallace multiplier using energy efficient CMOS full adder

Most fast computing applications required some arithmetic modules Multiplier is one of the most important module in such applications. Multipliers and their associated circuits like half adders, full



High-performance multiplexer-based logic synthesis using pass-transistor logic

  • Shen-Fu HsiaoJ. YehDa-Yen Chen
  • Engineering
    2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)
  • 2000
An automatic logic/circuit synthesizer is developed which takes as input several Boolean functions and generates netlist output with basic composing cells from the pass-transistor cell library

Top-down pass-transistor logic design

The results show that the area, delay, and power dissipation are improved by LEAP and that the value-cost ratio is improved by a factor of three, demonstrating that LEAP has the potential to achieve a quantum leap in value of LSI's while reducing the cost.

Cascode voltage switch logic: A differential CMOS logic family

A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described. A

A Fine Grain Configurable Logic Block for Self-checking FPGAs

This paper proposes a logic cell that can be used as a building block for Self-checking FPGAs and is self-checking for all single transistor stuck-on and stuck-off faults.

Design Methodology of a 32-bit Arithmetic Logic Unit with an Adaptive Leaf-cell Based Layout Technique

The architecture of the proposed 64-bit adder is based on the conditional select addition with regular adaptive multiplexers, and a shift algorithm with a pre-mask decoder is proposed for the 32-bit barrel shifter.

Low-Power Digital VLSI Design: Circuits and Systems

This paper presents a methodology for designing low-Voltage Low-Power VLSI CMOS Circuit Design that addresses the challenge of integrating low-voltage components into a coherent system.

Multiplexer-based Logic Synthesis Using Pass-transistor Logic

  • VLSI Design,
  • 2002

Lowpower digital VLSI design: circuits and systems

  • Lowpower digital VLSI design: circuits and systems

High - performance Multiplexerbased Logic Synthesis Using Passtransistor Logic ”

  • VLSI Design
  • 2002

Digital Integrated Circuits; a design prospective, Upper Saddle River

  • Digital Integrated Circuits; a design prospective, Upper Saddle River
  • 1996