Silicon nano-transistors and breaking the 10 nm physical gate length barrier

@article{Chau2003SiliconNA,
  title={Silicon nano-transistors and breaking the 10 nm physical gate length barrier},
  author={R. S. Chau and B. S. Doyle and Mark Doczy and Shammanna M. Datta and Scott Hareland and Ben Jin and Jack Kavalieros and Matthew J Metz},
  journal={61st Device Research Conference. Conference Digest (Cat. No.03TH8663)},
  year={2003},
  pages={123-126}
}
In this paper, the performance and energy delay trends for research devices down to 10 nm and also discusses the 10 nm barrier and potential ways to break it were explored. 
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References

Publications referenced by this paper.
Showing 1-3 of 3 references

Nikkei Microdevices

R. Chau
p.83-88, Feb. • 2002

hi-gate devices showing multiple legs

I l l R. Chau
Int. Conf. on Solid State Devices & Materials, • 2002

Silicon Nanoelectronics, Kyoto, Japan, p.2-3

R. Chau
2001

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