Silicon Debug and DFT for SOC IP


Nanometer circuits andfabrication process both are becoming increasingly complex at the same time. The very nature ofsilicon defects continue to evolve with these ground shift and are nowfocused on timing, signal integrity andprocess variations [1]. It is not enough to simply havefull scan ATPG vectors. There will be diagnostics built into the ATPG tools to fall back on when the ATPG tests fail, but these don't help debug timing defects and when thefail test data is compressed [2]. When yieldsfall and there is a danger to miss the TTM, TTP, TTx windows, the SOC integrator must be readyfor quick debug. Silicon Debug has evolved to be a process that requires planning, tools, and engineering resources. The basic DFTprinciples ofcontrollability and observability need to be extended to isolate afailing IP. Last but not the least, both SOC IP provider and integrator need to support diagnostics or Failure Analysis to zero-in on a defect. Nanometerfails require aparadigm shift, from Design -for-Test to Design-for-Debug. This tutorial will help the attendees recognize, enjoin and improve the Debug paradigm.

DOI: 10.1109/SOCC.2006.283910

Cite this paper

@inproceedings{Dakwala2006SiliconDA, title={Silicon Debug and DFT for SOC IP}, author={N. Dakwala}, booktitle={SoCC}, year={2006} }