Signal domain based reachability analysis in RTL circuits

@article{Bagri2015SignalDB,
  title={Signal domain based reachability analysis in RTL circuits},
  author={Sharad Bagri and Kelson Gent and Michael S. Hsiao},
  journal={Sixteenth International Symposium on Quality Electronic Design},
  year={2015},
  pages={250-256}
}
Register-transfer level (RTL) verification is a challenging problem for today's complex circuits. A sub-problem of verification is reachability of basic blocks or branches in the code. This paper proposes a novel analysis based on the domain of signal values in the RTL code to reason about the reachability of all branches without explicit circuit unrolling. This analysis takes into account all assignments, activating and preceding conditions in the code, to derive an assignment table that lists… CONTINUE READING
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