Signal-Margin-Screening for Multi-Mb MRAM

@article{Honigschmid2006SignalMarginScreeningFM,
  title={Signal-Margin-Screening for Multi-Mb MRAM},
  author={H. Honigschmid and Philipp Beer and Andreas Bette and R. Dittrich and R. Gardic and D. Gogl and Sezer Lammers and Jurgen Schmid and L. Altimime and S. Bournat and G S Muller},
  journal={2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers},
  year={2006},
  pages={467-476}
}
As MRAM technology is maturing, the need for developing a strategy to identify and replace marginal bits during read/write operation becomes necessary. The methodology and circuit techniques for read/write signal-margin screening implemented in a 0.18mum 16Mb MRAM design, are described. The methodology leads to increased read/write signal margins resulting in fully functional dice by applying a wafer-level screen test including half select disturb pattern 

From This Paper

Topics from this paper.

Citations

Publications citing this paper.
Showing 1-8 of 8 extracted citations

Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers • 2013
View 4 Excerpts
Highly Influenced

Vertical NV Memories an an Alternative to Scaling

2007 Non-Volatile Memory Technology Symposium • 2007
View 7 Excerpts
Highly Influenced

A 16-Mb Toggle MRAM With Burst Modes

IEEE Journal of Solid-State Circuits • 2007

MRAM Cell Technology for Over 500-MHz SoC

IEEE Journal of Solid-State Circuits • 2007
View 1 Excerpt

A 16Mb toggle MRAM with burst modes

2006 IEEE Asian Solid-State Circuits Conference • 2006
View 1 Excerpt

Adjacent-Reference and Self-Reference Sensing Scheme with Novel Orthogonal Wiggle MRAM Cell

2006 International Electron Devices Meeting • 2006
View 1 Excerpt

References

Publications referenced by this paper.
Showing 1-3 of 3 references

A 16Mb MRAM featuring bootstrapped write drivers

2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525) • 2004
View 2 Excerpts

A High-Speed 128kbit MRAM Core for Future Universal Memory Applications

A. Bette
Dig. Symp. on VLSI Circuits, pp. 217-220, June, 2003. • 2003
View 2 Excerpts

Magnetoresistive Random Access Memory Using Magnetic Tunnel Junctions

S. Tehrani
IEEE Proceedings, vol. 91, pp. 703-714, May, 2003. • 2003
View 2 Excerpts

Similar Papers

Loading similar papers…