Corpus ID: 233764990

Side-Channel Attacks on RISC-V Processors: Current Progress, Challenges, and Opportunities

@article{Ahmadi2021SideChannelAO,
  title={Side-Channel Attacks on RISC-V Processors: Current Progress, Challenges, and Opportunities},
  author={Mahya Morid Ahmadi and Faiq Khalid and Muhammad Akmal Shafique},
  journal={ArXiv},
  year={2021},
  volume={abs/2106.08877}
}
Side-channel attacks on microprocessors, like the RISC-V, exhibit security vulnerabilities that lead to several design challenges. Hence, it is imperative to study and analyze these security vulnerabilities comprehensively. In this paper, we present a brief yet comprehensive study of the security vulnerabilities in modern microprocessors with respect to side-channel attacks and their respective mitigation techniques. The focus of this paper is to analyze the hardware-exploitable side-channel… Expand

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References

SHOWING 1-10 OF 35 REFERENCES
Protecting RISC-V against Side-Channel Attacks
TLDR
This work made use of state of the art masking techniques and presented a novel solution to protect memory access against SCA by integrating side-channel analysis countermeasures into a RISC-V implementation, protecting against first-order power or electromagnetic attacks while keeping the implementation costs as low as possible. Expand
Replicating and Mitigating Spectre Attacks on a Open Source RISC-V Microarchitecture
Recent revelations of new side-channel vulnerabilities in modern processors has made hardware security a first-order concern in processor design. We demonstrate how the Berkeley Out-of-Order MachineExpand
Survey of Microarchitectural Side and Covert Channels, Attacks, and Defenses
TLDR
This survey extracts the key features of the processor’s microarchitectural functional units which make the channels possible, presents an analysis and categorization of the variety of microarch Architectural side and covert channels others have presented in literature, and surveys existing defense proposals. Expand
Winter is here! A decade of cache-based side-channel attacks, detection & mitigation for RSA
TLDR
This paper provides a detailed taxonomy of attacks on RSA cryptosystems and discusses their strengths and weaknesses while attacking different algorithmic implementations of RSA, and provides a classification of these attacks based on the source of information leakage. Expand
A high-resolution side-channel attack on last-level cache
TLDR
New techniques to achieve high-resolution tracking of the victim accesses to enable attacks on ciphers where critical events have a small cache footprint and it is shown that this attack frequently obtains an equal quality channel. Expand
Meet the Sherlock Holmes’ of Side Channel Leakage: A Survey of Cache SCA Detection Techniques
TLDR
A set of important characteristics are identified that can be used to characterize a CSCA (cache side channel attack) detection technique and some of the challenges the research community will have to resolve in future to improve the efficiency of cache side channel detection techniques. Expand
ARMageddon: Cache Attacks on Mobile Devices
TLDR
This work demonstrates how to solve key challenges to perform the most powerful cross-core cache attacks Prime+Probe, Flush+ Reload, Evict+Reload, and Flush-Flush on non-rooted ARM-based devices without any privileges. Expand
A Survey of Side-Channel Attacks on Caches and Countermeasures
TLDR
This paper surveys the widely used target encryption algorithms, the common attack techniques, and recent attacks that exploit the features of cache against the cloud computing and embedded systems, and surveys existing countermeasures at different abstraction levels. Expand
Cache Attacks and Countermeasures: The Case of AES
TLDR
An extremely strong type of attack is demonstrated, which requires knowledge of neither the specific plaintexts nor ciphertexts, and works by merely monitoring the effect of the cryptographic process on the cache. Expand
How secure is your cache against side-channel attacks?
  • Zecheng He, Ruby B. Lee
  • Computer Science
  • 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
  • 2017
TLDR
A novel probabilistic information flow graph is proposed to model the interaction between the victim program, the attacker program and the cache architecture, and a new metric, the Probability of Attack Success (PAS), is derived, which gives a quantitative measure for evaluating a cache’s resilience against a given class of cache side-channel attacks. Expand
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