Sharf: An FPGA-based customizable processor architecture

Abstract

This paper presents a general architecture for soft processors based on a modified Harvard architecture, SHARF. The separation of instruction and data path is extended by the concept of splitting application and control (address) specific computations. ALUs with any kind of operations and data types can be designed for a SHARF specific controller. Furthermore, an implementation of SIMD or VLIW systems is supported. In order to verify our concept, we have implemented an 18-bit controller according to the SHARF architecture and attached ALUs supporting variable data types and widths. The SHARF controller runs over 80 MHz and consumes about 200 slices. ALUs with common data types and widths were attached to the controller and compared with a standard CPU in terms of frequency, resource usage and runtime. For floating point data types the SHARF CPU requires up to 15% less resources running 10% faster.

DOI: 10.1109/FPL.2009.5272447

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