Serial and parallel interleaved modular multipliers on FPGA platform

@article{Javeed2015SerialAP,
  title={Serial and parallel interleaved modular multipliers on FPGA platform},
  author={Khalid Javeed and Xiaojun Wang and Mike Scott},
  journal={2015 25th International Conference on Field Programmable Logic and Applications (FPL)},
  year={2015},
  pages={1-4}
}
Modular multiplication is a core operation in all public key based cryptosystems. The performance of these cryptosystems can be enhanced substantially by incorporating an optimized modular multiplier. This paper presents serial and parallel radix-4 modular multipliers based on interleaved multiplication algorithm and Montgomery power laddering technique. A serial radix-4 interleaved modular multiplier provides 50% reduction in the required clock cycles. In addition to the reduction in clock… CONTINUE READING

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