Sequential circuit fault simulation using logic emulation

@article{Hwang1998SequentialCF,
  title={Sequential circuit fault simulation using logic emulation},
  author={Shih-Arn Hwang and Jin-Hua Hong and Cheng-Wen Wu},
  journal={IEEE Trans. on CAD of Integrated Circuits and Systems},
  year={1998},
  volume={17},
  pages={724-736}
}
A fast fault simulation approach based on ordinary logic emulation is proposed. The circuit configured into our system that emulates the faulty circuit’s behavior is synthesized from the good circuit and the given fault list in a novel way. Fault injection is made easy by shifting the content of a fault injection scan chain or by selecting the output of a parallel fault injection selector, with which we get rid of the time-consuming bit-stream regeneration process. Experimental results for… CONTINUE READING
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References

Publications referenced by this paper.
Showing 1-10 of 28 references

VLSI design of a cellular-automata based logic and fault simulator,

  • Y.-L. Li, Y.-C. Lai, C.-W. Wu
  • Proc. Nat. Sci. Council Part A: Phys. Sci. Eng…
  • 1997
3 Excerpts

An FPGA-based hardware emulator for fast fault emulation,

  • J.-H. Hong, S.-A. Hwang, C.-W. Wu
  • Proc. Midwest Symp. Circuits Syst
  • 1996
2 Excerpts

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