Semiconductor rams of the future

Abstract

Semiconductor memories have, since 1970, been a significant factor in data storage. This has been especially true in Random Access memories and is becoming true of the slower serial access memories. The manufacture of semiconductor memories takes place in two stages; the batch manufacture of the dice as wafers and the piece-by-piece assembly of the good dice into packages. It is the batch manufacturing of the dice that has led to the continuing trend of lower cost per bit. (Figure 1) With each new generation of memories, four factors have contributed to increased density of good bits per batch and therefore lower cost. These four factors are; decrease in storage cell complexity, decrease in feature size, increase in wafer size (thus batch size), and decrease in defect density. Decrease in storage cell complexity has been the most significant factor in increasing batch density. (Figure 2) An appropriate comparison of cell complexity can be made by expressing cell area in units of f2, where / is the minimum feature size allowed by the pattern-definition technology. Cell sizes in the last eight years have decreased from 200 f2 for the first static flip-flops to a present range of 16j2 to 20j2. It is theoretically possible to reach a cell 'size of 4j2 where there are two features in both the X and Y directions, one to store the information and the other to isolate it from adjacent cells. If means can be found to isolate adjacent cells in less than a feature size, then a cell size of /2 is possible. Added to the decrease in cell size is an inherent increase in layout efficiency. When memory size increases by a factor of four, only twice as many decoders, sense amplifiers, etc., are required; only two more address buffer circuits and the same number or less bonding pads are needed. A combination of design and process innovation has allowed this decrease in storage cell complexity, resulting in a 13.5 times increase in batch density. The second most significant of the four factors has been increased wafer size. As a result of a significant amount of development work on the equipment for manufacturing raw wafers and ·processing wafers, as well as developing processing techniques for handling larger wafers, the size of wafers has increased from two inches to four inches in diameter. This has resulted in a four times increase in wafer area and therefore a four times increase in batch density. The remaining two factors, feature size and defect density

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Cite this paper

@inproceedings{Bttcher2010SemiconductorRO, title={Semiconductor rams of the future}, author={C B{\"{o}ttcher}, year={2010} }