Semiconductor Materials Optimization for a TFET Device With Central Nothing Region on Insulator

  • Cristian Ravariu
  • Published 2013 in IEEE Transactions on Semiconductor Manufacturing

Abstract

This paper presents the work regimes of an atypical SOI device. The proposed device belongs to the Tunneling FET class, but the main body is a vacuum cavity. Each layer has a maximum of 10 nm. Firstly, the paper studies the static characteristics of the proposed device by simulations for different semiconductor materials: Si, SiC and Ge, with different… (More)

Topics

8 Figures and Tables

Statistics

0102020162017
Citations per Year

Citation Velocity: 7

Averaging 7 citations per year over the last 2 years.

Learn more about how we calculate this metric in our FAQ.

Slides referencing similar topics