Self-sampled vernier delay line for built-in clock jitter measurement

  title={Self-sampled vernier delay line for built-in clock jitter measurement},
  author={Kuo-Hsing Cheng and Chan-Wei Huang and Shu-Yu Jiang},
  journal={2006 IEEE International Symposium on Circuits and Systems},
  pages={4 pp.-1594}
For high-speed analog and mixed signal circuits, on-chip clock jitter measurement has been a challenge in recent years. Circuit resolution, chip area, and frequency range are critical specification for built-in-test (BIT) circuit design. In order to fulfil these requirements, the self-sampled Vernier delay line (VDL) structure is proposed. Comparing with traditional VDL structure, there is no more jitter free sample clock used in this design. When the proposed circuit is designed in 14 ps… CONTINUE READING


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