Self-reconfiguration on Spartan-III FPGAs with compressed partial bitstreams via a parallel configuration access port (cPCAP) core

@article{Bayar2008SelfreconfigurationOS,
  title={Self-reconfiguration on Spartan-III FPGAs with compressed partial bitstreams via a parallel configuration access port (cPCAP) core},
  author={Salih Bayar and Arda Yurdakul},
  journal={2008 Ph.D. Research in Microelectronics and Electronics},
  year={2008},
  pages={137-140}
}
This paper presents an alternative approach for dynamic partial self-reconfiguration that enables a field programmable gate array (FPGA) to reconfigure itself at run-time partially through a parallel configuration access port (cPCAP) under the control of the stand alone cPCAP core within the FPGA instead of using an embedded processor. The cPCAP core with bitstream decompression module needs only 361 slices, which is approximately 18% of a Spartan-3S200 FPGA. The dynamic partial self… CONTINUE READING
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