Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel

@article{Wong1997SelfalignedA,
  title={Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel},
  author={H.-S.P. Wong and K. Chan and Y. Taur},
  journal={International Electron Devices Meeting. IEDM Technical Digest},
  year={1997},
  pages={427-430}
}
  • H.-S.P. Wong, K. Chan, Y. Taur
  • Published 1997
  • Materials Science
  • International Electron Devices Meeting. IEDM Technical Digest
  • In this paper, we report a fabrication method that attains the "ideal" double-gate MOSFET device structure. The top and bottom gates are inherently self-aligned to the source/drain. The source/drain is a fanned-out source/drain structure, which provides a low parasitic resistance. Channel silicon thickness is determined by a planar film deposition process with good uniformity control in principle. N-channel double-gate MOSFET's with a 25 nm thick silicon channel were successfully demonstrated. 
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