Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel

  title={Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel},
  author={H.-S.P. Wong and K. Chan and Y. Taur},
  journal={International Electron Devices Meeting. IEDM Technical Digest},
  • H.-S.P. Wong, K. Chan, Y. Taur
  • Published 1997
  • Materials Science
  • International Electron Devices Meeting. IEDM Technical Digest
  • In this paper, we report a fabrication method that attains the "ideal" double-gate MOSFET device structure. The top and bottom gates are inherently self-aligned to the source/drain. The source/drain is a fanned-out source/drain structure, which provides a low parasitic resistance. Channel silicon thickness is determined by a planar film deposition process with good uniformity control in principle. N-channel double-gate MOSFET's with a 25 nm thick silicon channel were successfully demonstrated. 
    243 Citations

    Figures from this paper

    Strained-Si Channel Super-Self-Aligned Back-Gate/Double-Gate Planar Transistors
    • 3
    • PDF
    Two gates are better than one [double-gate MOSFET process]
    • 53
    Vertical Double-Gate MOSFET based on epitaxial growth by LPCVD
    • 8
    A Low-Power, Highly Scalable, Vertical Double-Gate MOSFET Using Novel Processes
    • 13
    Vertical p-channel double-gate MOSFETs
    • 8
    Fabrication of gate-all-around transistors using metal induced lateral crystallization
    • 12
    A Low Power, Highly Scalable, Vertical Double Gate MOSFET Using Novel Processes
    • 7
    Fabrication of raised S/D gate-all-around transistor and gate misalignment analysis
    • 14
    • Highly Influenced
    Nanoscale Triple Material Double Gate (TM-DG) MOSFET for Improving Short Channel Effects
    • P. Razavi, A.A. Orouji
    • Materials Science
    • 2008 International Conference on Advances in Electronics and Micro-electronics
    • 2008
    • 47