Self-Amplified Dual Gate Charge Trap Flash Memory for Low-Voltage Operation

@article{Jang2013SelfAmplifiedDG,
  title={Self-Amplified Dual Gate Charge Trap Flash Memory for Low-Voltage Operation},
  author={Ki-Hyun Jang and Hyun-June Jang and Jin-Kwon Park and Won-Ju Cho},
  journal={IEEE Electron Device Letters},
  year={2013},
  volume={34},
  pages={756-758}
}
We propose a self-amplified charge trap Flash memory using the dual-gate (DG) mode operation based on the capacitive coupling between the front-gate and back-gate as a promising next-generation nonvolatile memory. It is found that the coupling ratio and memory window strongly depend on the thickness of the buried oxide (BOX) layer in the silicon-on-insulator (SOI) substrate. As the BOX thickness of the SOI substrate increases, the coupling ratio and memory window of Flash memory cells increase… CONTINUE READING
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