Corpus ID: 235422569

Security Analysis of the Silver Bullet Technique for RowHammer Prevention

@article{Yagliki2021SecurityAO,
  title={Security Analysis of the Silver Bullet Technique for RowHammer Prevention},
  author={A. G. Yaglikçi and Jeremie S. Kim and Fabrice Devaux and O. Mutlu},
  journal={ArXiv},
  year={2021},
  volume={abs/2106.07084}
}
The purpose of this document is to study the security properties of the Silver Bullet algorithm against worst-case RowHammer attacks. We mathematically demonstrate that Silver Bullet, when properly configured and implemented in a DRAM chip, can securely prevent RowHammer attacks. The demonstration focuses on the most representative implementation of Silver Bullet, the patent claiming many implementation possibilities not covered in this demonstration. Our study concludes that Silver Bullet is a… Expand

Figures and Tables from this paper

References

SHOWING 1-10 OF 21 REFERENCES
RowHammer: A Retrospective
  • O. Mutlu, Jeremie S. Kim
  • Computer Science
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • 2020
TLDR
A principled approach to memory reliability and security research is described and advocated that can enable us to better anticipate and prevent vulnerabilities in DRAM and other types of memories, as the memory technologies scale to higher densities. Expand
Graphene: Strong yet Lightweight Row Hammer Protection
TLDR
Graphene is proposed, a low-cost Row Hammer prevention technique based on a space-efficient algorithm that identifies frequent elements from an incoming data stream that makes Graphene a scalable solution to Row Hammer attacks for the memory systems of today and the future. Expand
The RowHammer problem and other issues we may face as memory becomes denser
  • O. Mutlu
  • Computer Science
  • Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017
  • 2017
TLDR
This work discusses the RowHammer problem in DRAM, which is a prime (and perhaps the first) example of how a circuit-level failure mechanism can cause a practical and widespread system security vulnerability, and describes and advocates a principled approach to memory reliability and security research that can enable us to better anticipate and prevent such vulnerabilities. Expand
TWiCe: Preventing Row-hammering by Exploiting Time Window Counters
TLDR
This paper proposes a new counter-based RH prevention solution named Time Window Counter (TWiCe) based row refresh, which accurately detects potential RH attacks only using a small number of counters with a minimal performance impact. Expand
TRRespass: Exploiting the Many Sides of Target Row Refresh
TLDR
The inner workings of TRR are demystified, which shows that what is advertised as a single mitigation mechanism is actually a series of different solutions coalesced under the umbrella term Target Row Refresh, and it is demonstrated that modern implementations operate entirely inside DRAM chips. Expand
BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows
TLDR
The key idea of BlockHammer is to track row activation rates using area-efficient Bloom filters, and use the tracking data to ensure that no row is ever activated rapidly enough to induce RowHammer bit-flips. Expand
Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques
TLDR
Five state-of-the-art RowHammer mitigation mechanisms are evaluated using cycle-accurate simulation in the context of real data taken from chips to study how the mitigation mechanisms scale with chip vulnerability, and it is found that existing mechanisms either are not scalable or suffer from prohibitively large performance overheads in projected future devices. Expand
Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors
  • Yoongu Kim, Ross Daly, +6 authors O. Mutlu
  • Computer Science
  • 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)
  • 2014
TLDR
This paper exposes the vulnerability of commodity DRAM chips to disturbance errors, and shows that it is possible to corrupt data in nearby addresses by reading from the same address in DRAM by activating the same row inDRAM. Expand
Experiments and root cause analysis for active-precharge hammering fault in DDR3 SDRAM under 3 × nm technology
TLDR
Investigation of the failure mechanism manifested in DDR3 SDRAMs under 3 × nm technology finds that the charge in a DRAM cell leaked faster, and the values of the stressed cells could not be retained with valid yet stressful hammered accesses to a row. Expand
Trap-Assisted DRAM Row Hammer Effect
Through 3D TCAD simulations with single charge traps, we discovered a direct evidence to the mechanism of DRAM row hammer effect. It is governed by a charge pumping process, consisting of chargeExpand
...
1
2
3
...