Securing Scan Design Using Lock and Key Technique

  title={Securing Scan Design Using Lock and Key Technique},
  author={Jeremy Lee and Mark Mohammad Tehranipoor and Chintan Patel and James F. Plusquellic},
  journal={20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)},
Scan test has been a common and useful method for testing VLSI designs due to the high controllability and observability it provides. These same properties have recently been shown to also be a security threat to the intellectual property on a chip (Yang et al., 2004). In order to defend from scan based attacks, we present the lock & key technique. Our proposed technique provides security while not negatively impacting the design's fault coverage. This technique requires only that a small area… CONTINUE READING
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