Securing Scan Design Using Lock and Key Technique

@article{Lee2005SecuringSD,
  title={Securing Scan Design Using Lock and Key Technique},
  author={Jeremy Lee and Mark Mohammad Tehranipoor and Chintan Patel and James F. Plusquellic},
  journal={20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)},
  year={2005},
  pages={51-62}
}
Scan test has been a common and useful method for testing VLSI designs due to the high controllability and observability it provides. These same properties have recently been shown to also be a security threat to the intellectual property on a chip (Yang et al., 2004). In order to defend from scan based attacks, we present the lock & key technique. Our proposed technique provides security while not negatively impacting the design's fault coverage. This technique requires only that a small area… CONTINUE READING
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References

Publications referenced by this paper.
Showing 1-10 of 22 references

The Best-Laid Boards

  • S. Scheiber
  • Apr. 2005. [Online]. Available: http://www…
  • 2005
2 Excerpts

Scan Design Called Portal for Hackers

  • R. Goering
  • Oct. 2004. [Online]. Available: http://www…
  • 2004
2 Excerpts

User Manual for Synopsys Toolset Version 2004.06

  • Synopsys DFT Compiler
  • Synopsys Inc., 2004.
  • 2004
1 Excerpt

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