Secure Logic Synthesis

@inproceedings{Tiri2004SecureLS,
  title={Secure Logic Synthesis},
  author={K. Tiri and I. Verbauwhede},
  booktitle={FPL},
  year={2004}
}
This paper describes the synthesis of dynamic differential logic to increase the resistance of FPGAs against Differential Power Analysis. Compared with an existing technique, it saves more than a factor 2 in slice utilization. Experimental results indicate that a secure version of the AES algorithm can now be implemented with a mere doubling of the slice utilization when compared with a normal non-secure single ended implementation. 
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TLDR
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References

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Synthesis of Secure FPGA Implementations
TLDR
The synthesis of Dynamic Differential Logic to increase the resistance of FPGA implementations against Differential Power Analysis and indicates that a secure version of the AES encryption algorithm can now be implemented with a mere 50% increase in time delay and 90% increase on slice utilization when compared with a normal non-secure single ended implementation. Expand
A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation
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  • Computer Science
  • Proceedings Design, Automation and Test in Europe Conference and Exhibition
  • 2004
TLDR
A novel design methodology to implement a secure DPA resistant crypto processor that combines standard building blocks to make 'new' compound standard cells, which have a close to constant power consumption. Expand
How Secure Are FPGAs in Cryptographic Applications?
TLDR
This contribution appears to be the first comprehensive treatment of system and security aspects of cryptographic schemes implemented on FPGAs. Expand
Power-Analysis Attacks on an FPGA - First Experimental Results
TLDR
This paper is the first to describe a setup to conduct power-analysis attacks on FPGAs, and provides strong evidence that implementations of elliptic curve cryptosystems without specific countermeasures are indeed vulnerable to simple power- analysis attacks. Expand
Dynamic power consumption in Virtex™-II FPGA family
TLDR
The dynamic power consumption in the fabric of Field Programmable Gate Arrays (FPGAs) is analyzed by taking advantage of both simulation and measurement, and it is concluded that dynamic power dissipation of a Virtex-II CLB is 5.9μW per MHz for typical designs, but it may vary significantly depending on the switching activity. Expand
Synthesis of Secure FPGA Implementations UCLA Internal report, available as report 2004/068 from the IACR Cryptology ePrint Archive
  • Synthesis of Secure FPGA Implementations UCLA Internal report, available as report 2004/068 from the IACR Cryptology ePrint Archive
  • 2004