Secure Logic Synthesis

  title={Secure Logic Synthesis},
  author={K. Tiri and I. Verbauwhede},
This paper describes the synthesis of dynamic differential logic to increase the resistance of FPGAs against Differential Power Analysis. Compared with an existing technique, it saves more than a factor 2 in slice utilization. Experimental results indicate that a secure version of the AES algorithm can now be implemented with a mere doubling of the slice utilization when compared with a normal non-secure single ended implementation. 
Secured-by-design FPGA: look-up tables and switch-boxes
  • Ziyad Almohaimeed, M. Sima
  • Computer Science
  • 2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)
  • 2015
A circuit technique based on hardware replication improves the robustness of the FPGA circuitry against dynamic and/or static power attacks and exhibits an increased robustness against early evaluation attacks and those based on glitches. Expand
Look-Up tables with multiple inputs for secured-by-design FPGAs
  • Ziyad Almohaimeed, M. Sima
  • Computer Science
  • 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)
  • 2016
We introduce a set of circuit techniques that make the dynamic and static power consumptions of multiple-input Look-Up Tables (LUT) independent of both the input data and FPGA configuration. ThisExpand
Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic
Methods to reduce the size of wave dynamic differential logic (WDDL) implementations and it is shown that linear parts of algorithms can be delegated to a synthesizer, but that non-linear parts are better off to be handled with heuristics. Expand
Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs
This work investigates "wave dynamic differential logic'' (WDDL), a logic-level counter-measure based on leakage hiding thanks to balanced dual-rail logic, and reports a CAD methodology for achieving WDDL in FPGA. Expand
SCAR-FPGA : A novel side-channel attack resistant fpga
In design of embedded systems for security applications, flexibility and tamper-resistance are two important factors to be considered. High frequency of updates and high costs of ASIC and their longExpand
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints
A preprocessing method to improve side channel attacks (SCAs) on dual-rail with precharge logic (DPL) countermeasure family by attacking a DES cryptoprocessor embedded in a field programmable gates array (FPGA), and protected by the wave dynamic differential logic (WDDL)countermeasure. Expand
FPGA Implementation of pAsynch Design Paradigm
This paper focuses on the practical implementation of pAsynch protection scheme on FPGA, overcoming some of the inherent challenges associated with the clocking scheme that is the basis of this technique. Expand
Survey of Methods to Improve Side-Channel Resistance on Partial Reconfigurable Platforms
This survey discusses how the countermeasures, known from literature, can be applied on FPGA-based systems to improve the side-channel resistance and discusses the hiding-based countermeasure against power analysis attacks especially designed for reconfigurable FPGAs. Expand
Place-and-route impact on the security of DPL designs in FPGAs
  • S. Guilley, S. Chaudhuri, +5 authors V. Vong
  • Engineering, Computer Science
  • 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
  • 2008
To which extent the differential place-and-route constraints must be strict in FPGA technology is studied and Xilinx fitting tool achieves naturally good balancing results, leading to unprecedented dual netlists balancing. Expand
A Progressive Dual-Rail Routing Repair Approach for FPGA Implementation of Crypto Algorithm
A novel implementation approach applied to a complete AES-128 crypto algorithm which splits the whole algorithm to submodules and transform individuals to DPL format respectively, and shows a greatly elevated success rate during the routing repair phase. Expand


Synthesis of Secure FPGA Implementations
The synthesis of Dynamic Differential Logic to increase the resistance of FPGA implementations against Differential Power Analysis and indicates that a secure version of the AES encryption algorithm can now be implemented with a mere 50% increase in time delay and 90% increase on slice utilization when compared with a normal non-secure single ended implementation. Expand
A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation
  • K. Tiri, I. Verbauwhede
  • Computer Science
  • Proceedings Design, Automation and Test in Europe Conference and Exhibition
  • 2004
A novel design methodology to implement a secure DPA resistant crypto processor that combines standard building blocks to make 'new' compound standard cells, which have a close to constant power consumption. Expand
How Secure Are FPGAs in Cryptographic Applications?
This contribution appears to be the first comprehensive treatment of system and security aspects of cryptographic schemes implemented on FPGAs. Expand
Power-Analysis Attacks on an FPGA - First Experimental Results
This paper is the first to describe a setup to conduct power-analysis attacks on FPGAs, and provides strong evidence that implementations of elliptic curve cryptosystems without specific countermeasures are indeed vulnerable to simple power- analysis attacks. Expand
Dynamic power consumption in Virtex™-II FPGA family
The dynamic power consumption in the fabric of Field Programmable Gate Arrays (FPGAs) is analyzed by taking advantage of both simulation and measurement, and it is concluded that dynamic power dissipation of a Virtex-II CLB is 5.9μW per MHz for typical designs, but it may vary significantly depending on the switching activity. Expand
Synthesis of Secure FPGA Implementations UCLA Internal report, available as report 2004/068 from the IACR Cryptology ePrint Archive
  • Synthesis of Secure FPGA Implementations UCLA Internal report, available as report 2004/068 from the IACR Cryptology ePrint Archive
  • 2004