SeaStar Interconnect: Balanced Bandwidth for Scalable Performance

@article{Brightwell2006SeaStarIB,
  title={SeaStar Interconnect: Balanced Bandwidth for Scalable Performance},
  author={R. Brightwell and K. Pedretti and K. Underwood and T. Hudson},
  journal={IEEE Micro},
  year={2006},
  volume={26},
  pages={41-57}
}
The Seastar, a new ASIC from Cray, is a full system-on-chip design that integrates high-speed serial links, a 3D router, and traditional network interface functionality, including an embedded processor in a single chip. Cray Inc. designed the SeaStar specifically to support Sandia National Laboratories' ASC Red Storm, a distributed-memory parallel computing platform containing more than 11,000 network end-points. SeaStar presented designers with several challenging goals that were commensurate… Expand
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