Scheduling Coarse-Grain Operations for VLIW Processors

  title={Scheduling Coarse-Grain Operations for VLIW Processors},
  author={Natalino G. Bus{\'a} and Albert van der Werf and Marco Bekooij},
In order to speed up current DSP applications, complex hardware accelerators may be added in DSP architectures. This means that "coarse-grain " operations, characterized by a long latency and by a complex Input-Output timeshape, may be available to implement the given application. In a traditional scheduling approach, coarse-grain operations are treated as bulky atomic multi-cycle operations, under the worst case assumption that inputs and output are confined at the beginning and at the end of… CONTINUE READING