Schedule-Sensitive Register Pressure Reduction in Innermost Loops, Basic Blocks and Super-Blocks

@inproceedings{Briais2009ScheduleSensitiveRP,
  title={Schedule-Sensitive Register Pressure Reduction in Innermost Loops, Basic Blocks and Super-Blocks},
  author={S{\'e}bastien Briais and Sid Touati},
  year={2009}
}
This report makes a massive experimental study of an efficient heuristic for the SIRA framework \cite{sira04}. The heuristic, called SIRALINA \cite{siralina07}, bounds the register requirement of a data dependence graph before instruction scheduling under resource constraints. Our aim is to guarantee the absence of spilling before any instruction scheduling process, without hurting instruction level parallelism if possible. Our register pressure reduction methods are sensitive for both software… CONTINUE READING

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