Scaling to the end of silicon with EDGE architectures

  title={Scaling to the end of silicon with EDGE architectures},
  author={Doug Burger and Stephen W. Keckler and Kathryn S. McKinley and Michael Dahlin and Lizy Kurian John and Calvin Lin and Charles R. Moore and James H. Burrill and Robert G. McDonald and William Yode},
Microprocessor designs are on the verge of a post-RISC era in which companies must introduce new ISAs to address the challenges that modern CMOS technologies pose while also exploiting the massive levels of integration now possible. To meet these challenges, we have developed a new class of ISAs, called explicit data graph execution (EDGE), that will match the characteristics of semiconductor technology over the next decade. The TRIPS architecture is the first instantiation of an EDGE… CONTINUE READING
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Data Flow Languages and Architecture

  • T. N. Vijaykumar
  • Proc . 8 th Int ’ l Symp . Computer Architecture
  • 1995

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