Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's

  title={Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's},
  author={C. P. Auth and J B Plummer},
  journal={IEEE Electron Device Letters},
We present a scaling theory for fully-depleted, cylindrical MOSFET's. This theory was derived from the cylindrical form of Poisson's equation by assuming a parabolic potential in the radial direction. Numerical device simulation data for subthreshold slope and DIBL were compared to the model to validate the formula. By employing the scaling theory a comparison with double-gate (DG) MOSFET's was carried out illustrating an improvement of up to 40% in the minimum effective channel length for the… CONTINUE READING
Highly Influential
This paper has highly influenced 19 other papers. REVIEW HIGHLY INFLUENTIAL CITATIONS
Highly Cited
This paper has 346 citations. REVIEW CITATIONS

From This Paper

Figures, tables, results, connections, and topics extracted from this paper.
170 Extracted Citations
15 Extracted References
Similar Papers

Citing Papers

Publications influenced by this paper.
Showing 1-10 of 170 extracted citations

347 Citations

Citations per Year
Semantic Scholar estimates that this publication has 347 citations based on the available data.

See our FAQ for additional information.

Referenced Papers

Publications referenced by this paper.
Showing 1-10 of 15 references

Scaling theory of double-gate SOI MOSFET’s

  • K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, Y. Arimoto
  • IEEE Trans. Electron Devices , vol. 40, pp. 2326…
  • 1993
Highly Influential
3 Excerpts

Analysis of conduction in fully depleted SOI MOS- FET’s

  • K. K. Young
  • IEEE Trans. Electron Devices , vol. 36, pp. 504…
  • 1989
Highly Influential
3 Excerpts

A novel circuit technology with surrounding gate transistors (SGT’s) for ultra- high density DRAM’s

  • S. Watanabe, K. Tsuchida, +9 authors H. Hara
  • IEEE. J. Solid-State Circuits, vol. 30, pp. 960…
  • 1995

Impact of a vertical -shape transistor (V T) cell for 1 Gbit DRAM and beyond,”IEEE

  • S. Maeda, S. Maegawa, +6 authors N. Tsubouchi
  • Trans. Electron Devices ,
  • 1995
1 Excerpt

Scaling the MOS transistor below 0.1 m: Methodology, device structures, and technology requirements

  • C. Fiegna, H. Iwai, T. Wada, M. Saito, E. Sangiorgi, B. Ricco
  • IEEE Trans. Electron Devices , vol. 41, pp. 941…
  • 1994

Scaling the Si MOSFET : From bulk to SOI to bulk

  • K. Suzuki Tosaka, T. Sugii
  • IEEE Trans . Electron Devices
  • 1993

Monte Carlo simulation of a 30 nm dual-gate MOSFET: How short can Si go

  • D. Frank, S. Laux, M. Fischetti
  • IEDM Tech. Dig. , 1992, pp. 553–556.
  • 1992
1 Excerpt

Scaling the Si MOSFET: From bulk to SOI to bulk,”IEEE

  • R. H. Yan, A. Ourmazd, K. F. Lee
  • Trans. Electron Devices ,
  • 1992
1 Excerpt

Similar Papers

Loading similar papers…