Scaling of advanced floating body Z-RAM storage cells: A modeling approach

@article{Sverdlov2009ScalingOA,
  title={Scaling of advanced floating body Z-RAM storage cells: A modeling approach},
  author={Viktor Sverdlov and Siegfried Selberherr},
  journal={2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)},
  year={2009},
  pages={185-188}
}
A modeling approach to study advanced floating body Z-RAM memory cells is developed. In particular, the scalability of the cells is investigated. First, a Z-RAM cell based on a 50nm gate length double-gate structure corresponding to state of the art technology is studied. A bi-stable behavior essential for Z-RAM operation is observed even in fully depleted structures. It is demonstrated that by adjusting the supply source-drain and gate voltages the programming window can be adjusted. The… CONTINUE READING

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References

Publications referenced by this paper.
SHOWING 1-10 OF 28 REFERENCES

and E

M. V. Fischetti, S. E. Laux
  • Crabbé, “Understanding Hot-Electron Transport in Silicon Devices: Is there a Shortcut?” J.Appl.Phys., vol. 78, no. 2, pp. 1058–1085
  • 1995
VIEW 5 EXCERPTS
HIGHLY INFLUENTIAL

Kencke, and P.L.D. Chang, “A Scaled Floating Body Cell (FBC) Memory with High-k+Metal Gate on Thin-Silicon and Thin-BOX for 16nm Technology Node and Beyond,

D. Ban, D.L.U.E. Avci
  • VLSI Symposium,
  • 2008

P

M. G. Ertosun, H. Cho
  • Kapur, and K.C. Saraswat, “A Nanoscale Vertical Double-Gate Single-Transistor Capacitorless DRAM,” IEEE Electron Device Lett., vol. 29, no. 6, pp. 615–617
  • 2008

P

M. G. Ertosun, H. Cho
  • Kapur, and K.C. Saraswat, “A Nanoscale Vertical Double-Gate Single-Transistor Capacitorless DRAM,” IEEE Electron Device Lett., vol. 29, no. 6, pp. 615–617
  • 2008

and P

U. Avci, I. Ban, D. Kencke
  • Chang,”Floating Body Cell (FBC) Memory for 16-nm Technology with Low Variation on Thin Silicon and 10-nm BOX”, in Proceedings IEEE International SOI Conference
  • 2008
VIEW 1 EXCERPT