ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation

@article{Ye2021ScaleHLSAN,
  title={ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation},
  author={Hanchen Ye and Cong Hao and Jianyi Cheng and Hyunmin Jeong and Jack Huang and Stephen Neuendorffer and Deming Chen},
  journal={2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)},
  year={2021},
  pages={741-755}
}
  • Hanchen YeCong Hao Deming Chen
  • Published 24 July 2021
  • Computer Science
  • 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
High-level synthesis (HLS) has been widely adopted as it significantly improves the hardware design productivity and enables efficient design space exploration (DSE). Existing HLS tools are built using compiler infrastructures largely based on a single-level abstraction, such as LLVM. How-ever, as HLS designs typically come with intrinsic structural or functional hierarchies, different HLS optimization problems are often better solved with different levels of abstractions. This paper proposes… 

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