ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation

@article{Ye2021ScaleHLSAN,
  title={ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation},
  author={Hanchen Ye and Cong Hao and Jianyi Cheng and Hyunmin Jeong and Jack Huang and Stephen Neuendorffer and Deming Chen},
  journal={2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)},
  year={2021},
  pages={741-755}
}
  • Hanchen YeCong Hao Deming Chen
  • Published 24 July 2021
  • Computer Science
  • 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
High-level synthesis (HLS) has been widely adopted as it significantly improves the hardware design productivity and enables efficient design space exploration (DSE). Existing HLS tools are built using compiler infrastructures largely based on a single-level abstraction, such as LLVM. How-ever, as HLS designs typically come with intrinsic structural or functional hierarchies, different HLS optimization problems are often better solved with different levels of abstractions. This paper proposes… 
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13 Citations
Highly Influential Citations
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Background Citations
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Methods Citations
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Results Citations
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13 Citations

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An MLIR-based Compiler Flow for System-Level Design and Hardware Acceleration

SODA-OPT, a compiler tool that extends the MLIR infrastructure, is introduced and the practical applicability of the compilation flow is demonstrated by exploring the automatic generation of accelerators for deep neural networks operators outlined at arbitrary granularity and by combining outlining with tiling on large convolution layers.

The Support of MLIR HLS Adaptor for LLVM IR

This paper proposes an adaptor for LLVM IR, which can optimize the IR, generated from MLIR, into HLS readable IR, without the gap of unsupported syntax between different versions, so developers could focus on their specialization.

Bridging Python to Silicon: The SODA Toolchain

The software-defined accelerator (SODA) synthesizer is presented, a modular and open-source hardware compiler that provides automated end-to-end synthesis from high-level software frameworks to ASIC implementation, relying on multilevel representations to progressively lower and optimize the input code.

POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations

POLSCA is a compiler framework that improves polyhedral HLS workflow by automatic code transformation, decomposing a design before polyhedral optimization to balance code complexity and parallelism, while revising memory interfaces of polyhedral-transformed code to make partitioning explicit for HLS tools.

DeepFlexiHLS: Deep Neural Network Flexible High-Level Synthesis Directive Generator

DeepFlexiHLS, a two-stage design space exploration flow to find a set of directives to achieve minimal latency, and forms a Pareto-frontier from which the designer can choose if FPGA resources are limited or are not to be entirely used by the DNN module.

Auto-Partitioning Heterogeneous Task-Parallel Programs with StreamBlocks

This work introduces StreamBlocks, a unified open-source software/FPGA compiler and runtime that takes dataflow programs written in Cal, and automatically partitions them across heterogeneous CPU/ FPGA platforms, and achieves a 4 -- 7× speedup over trivial partitions.

OpenHLS: High-Level Synthesis for Low-Latency Deep Neural Networks for Experimental Science

An open source, lightweight, compiler framework, without any proprietary dependencies, OpenHLS, based on high-level synthesis techniques, for translating high- level representations of deep neural networks to low-level representations, suitable for deployment to near-sensor devices such as field-programmable gate arrays.

Compilation and Optimizations for Efficient Machine Learning on Embedded Systems

A series of e-ective design methodologies, including e-cient ML model designs, customized hardware accelerator designs, and hard-ware/software co-design strategies to enable e-scientific ML applications on embedded systems are introduced.

FSLAM: an Efficient and Accurate SLAM Accelerator on SoC FPGAs

An FPGA based ORB-SLAM system, named FSLAM, that accelerates the computationally intensive visual feature extraction and matching on hardware that achieves high accuracy with reduced computational complexity.

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