Scalably-Verifiable Sequential Synthesis

  • Robert Brayton Alan Mishchenko
  • Published 2007


This report is a case-study of the synergy between sequential synthesis and verification. Described is an efficient implementation of a sequential synthesis that uses simple induction to detect and merge sequentially-equivalent registers and nodes in a sequential circuit with a given initial state. Since retiming is not performed, state-encoding, scan… (More)

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