Scalable shared-memory multiprocessor architectures

@article{Thakkar1990ScalableSM,
  title={Scalable shared-memory multiprocessor architectures},
  author={Shreekant S. Thakkar and Michel Dubois and Anthony T. Laundrie and Gurindar S. Sohi and David V. James and Stein Gjessing and Manu Thapar and Bruce Delagi and Michael J. Carlton and Alvin M. Despain},
  journal={Computer},
  year={1990},
  volume={23},
  pages={71-74}
}
Directory-based and bus-based cache coherence schemes are defined and described. Directory-based schemes can be classified as centralized or distributed. Both categories support local caches to improve processor performance and reduce traffic in the interconnection. Schemes using presence flags, B pointers, and linked lists are discussed. Bus-based systems provide uniform memory access to all processors. This memory organization allows a simpler programming model, making it easier to develop… 
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The M2 hierarchical multiprocessor
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TLDR
A scalable snoopy scheme based on a single-hop-connected multiple-bus topology that can enjoy fast memory access and can also take advantage of greater scalability, and whose number of transceivers can grow naturally with the number of processors in the system.
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TLDR
This dissertation investigates ways to efficiently share frequently changing data among thousands of processors using Scalable Coherent Interface (SCI), and investigates two new cache-coherence protocols that employ trees of cache lines and have similar or lower latency than SCI.
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This paper addresses issues and describes solutions of how to take advantage of the fast data transmission among memories to implement large SVM address spaces on large-scale multicomputers.
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The design and development of a bus-based hierarchical multiprocessor named M/sup 2/ is discussed, which features a much higher degree of scalability than the shared-memory shared-bus architecture and exploits parallelism at both medium- and coarse-grain levels.
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