Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning
Multi-core processors have become common in current computing platforms. Today, most of multi-core workstations and PCs have adopted NUMA (Non-Uniform Memory Access) advanced memory architecture for high performance and scalability. In response, EDA (Electronic Design Automation) community has applied significant effort to parallelize many EDA algorithms with some success. However, event-driven simulation of designs modeled in HDL (Hardware Description Language) has not achieved meaningful progress so far. This paper proposes a highly scalable parallel, event-driven HDL simulation method, based upon accurate stimulus prediction. The paper presents the basic idea of this approach and discusses why this new method is ideally positioned for achieving high parallelism with NUMA architecture.