Scalable hardware memory disambiguation for high ILP processors

@article{Sethumadhavan2003ScalableHM,
  title={Scalable hardware memory disambiguation for high ILP processors},
  author={Simha Sethumadhavan and Rajagopalan Desikan and Doug Burger and Charles R. Moore and Stephen W. Keckler},
  journal={Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36.},
  year={2003},
  pages={399-410}
}
This paper describes several methods for improving the scalability of memory disambiguation hardware for future high ILP processors. As the number of in-flight instructions grows with issue width and pipeline depth, the load/store queues (LSQ) threaten to become a bottleneck in both power and latency. By employing lightweight approximate hashing in hardware with structures called Bloom filters, many improvements to the LSQ are possible. We propose two types of filtering schemes using Bloom… 
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