Scalable and parameterised VLSI architecture for efficient sparse approximation in FPGAs and SoCs

@inproceedings{Ren2013ScalableAP,
  title={Scalable and parameterised VLSI architecture for efficient sparse approximation in FPGAs and SoCs},
  author={Fengbo Ren and Weiqiang Xu},
  year={2013}
}
Techset Com A parameterised and scalable very large scale integration (VLSI) soft intellectual property (IP) is presented that can be implemented in programmable logic devices, such as field programmable gate arrays (FPGAs) or a system-on-chip design for efficient sparse approximation. The proposed architecture is optimised based on the orthogonal matching pursuit algorithm by both algorithm reformulation and architecture resource sharing techniques. The soft IP core supports a floating-point… CONTINUE READING