Scalable Architectures for Design of Reversible Quaternary Multiplexer and Demultiplexer Circuits

Abstract

Quaternary reversible logic is very suitable for encoded realization of binary reversible logic functions by grouping two bits together into quaternary digits. Quaternary multiplexer and demultiplexer circuits are very important building blocks of quaternary digital systems. In this paper, we show reversible realizations of 4x1 multiplexer and 1x4… (More)
DOI: 10.1109/ISMVL.2009.26

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