Scalable Antirandom Testing ( SAT )

@inproceedings{SahariScalableAT,
  title={Scalable Antirandom Testing ( SAT )},
  author={Muhammad Sadiq Sahari and Abu Khari A’ain}
}
— Antirandom testing approach requires large input space and complex test vector generation algorithm when used on circuit under test (CUT) with large number of inputs. In this work, we proposed a novel and simple approach of Antirandom sequence generation by using the least significant bit (LSB) of the test vector as a reference to generate the next test vector. Fault simulations on ISCAS'85 benchmark circuits shown that a high fault coverage for combinational logic circuits has been obtained… CONTINUE READING