Scalability of strained-Si nMOSFETs down to 25 nm gate length

@article{Goo2003ScalabilityOS,
  title={Scalability of strained-Si nMOSFETs down to 25 nm gate length},
  author={Jung-Suk Goo and Qi Xiang and Yayoi Takamura and Haihong Wang and J. Pan and Farzad Arasnia and E. Paton and Paul R. Besser and M. V. Sidorov and Ercan Adem and Anthony Lochtefeld and G. R. Braithwaite and M. Currie and R D Hammond and M. Bulsara and Ming-Ren Lin},
  journal={IEEE Electron Device Letters},
  year={2003},
  volume={24},
  pages={351-353}
}
Strained-Si nMOSFETs with a standard polysilicon gate process were fabricated down to 25 nm gate length with well-behaved characteristics and small difference in short channel effects. The performance enhancement degrades linearly as the gate length becomes shorter, due to not only the parasitic resistance but also heavy halo implant. Thus the key integration issues are how to manage threshold difference and As diffusion without excess doping. With comparable doping and well controlled… CONTINUE READING
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Interfacial reactions of Ni on SiGe (x = 0:2, 0.3) at low temperature by rapid thermal annealing

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