SWAN: high-level simulation methodology for digital substrate noise generation

@article{Badaroglu2006SWANHS,
  title={SWAN: high-level simulation methodology for digital substrate noise generation},
  author={Mustafa Badaroglu and Geert Van der Plas and Piet Wambacq and St{\'e}phane Donnay and Georges G. E. Gielen and Hugo De Man},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2006},
  volume={14},
  pages={23-33}
}
Substrate noise generated by the switching digital circuits degrades the performance of analog circuits embedded on the same substrate. It is therefore important to know the amount of noise at a certain point on the substrate. Existing transistor-level simulation approaches based on a substrate model extracted from layout information are not feasible for digital circuits of practical size. This paper presents a complete high-level methodology, which simulates a large digital standard cell-based… CONTINUE READING

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