STV-Cache: a leakage energy-efficient architecture for data caches

  title={STV-Cache: a leakage energy-efficient architecture for data caches},
  author={Kimish Patel and Luca Benini and Enrico Macii and Massimo Poncino},
  booktitle={ACM Great Lakes Symposium on VLSI},
We propose a low-leakage cache architecture based on the observation of the spatio-temporal properties of data caches. In particular, we exploit the fact that during the program lifetime a few data values tend to exhibit both spatial and temporal locality in cache, i.e., values that are simultaneously stored by several lines at the same time. Leakage energy can be reduced by turning off those lines and storing these values in a smaller, separate memory. In this work we introduce an architecture… CONTINUE READING