Multi-level reconfigurable architectures in the switch model
Dynamically reconfigurable hardware offers promising possibilities for flexible, computation intensive applications. With the technological advance of reconfigurable hardware came a rapid growth in the number of resources per chip requiring large amounts of data transfer per reconfiguration. Especially run-time reconfigurable applications, which make frequent use of reconfiguration, suffer from the growing overhead induced thereby. In this project, we investigate novel concepts for reconfigurable architectures that can dynamically reconfigure the actual reconfiguration potential to reduce the total amount of reconfiguration data that is necessary for a computation.