SPADES: a simulator for path delay faults in sequential circuits

Abstract

A fault simulator for path delay faults in synchronous sequential circuits is described, where a test sequence is considered under di~erent combinations of slow and fast clock cycles (clocking schemes). The novel features of the simulator are: (1) multiple clocking schemes used for the application of a given test sequence are considered in parallel… (More)

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Cite this paper

@inproceedings{Pomeranz1992SPADESAS, title={SPADES: a simulator for path delay faults in sequential circuits}, author={Irith Pomeranz and Lakshmi N. Reddy and Sudhakar M. Reddy}, booktitle={EURO-DAC}, year={1992} }