• Corpus ID: 17336183

SPACE TIME SCHEDULING STRATEGY FOR EFFICIENT 2-D DCT ARCHITECTURE 1

@inproceedings{KiruthikaSPACETS,
  title={SPACE TIME SCHEDULING STRATEGY FOR EFFICIENT 2-D DCT ARCHITECTURE 1},
  author={Kiruthika and Sivanthiram}
}
Distributed arithmetic (DA) has been generally used to apply inner product calculation with a fixed input. Conventional ROM-based DA suffers from large ROM requirements. A new DA algorithm is used to expand the fixed input as an alternative of the variable input into bit level as in ROM-based DA. Thus the new DA algorithm can take advantage of shared partial sum-of-products and sparse non zero bits in the fixed input to reduce the number of computation. Unlike ROM based DA that stores the pre… 

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References

SHOWING 1-10 OF 22 REFERENCES

Shift-Register-Based Data Transposition for Cost-Effective Discrete Cosine Transform

TLDR
A new schedule for 2-D-DCT computing to reduce the hardware cost and the memory size can be greatly reduced, and the address generator and its READ/WRITE control all can be saved.

A cost-effective architecture for 8×8 two-dimensional DCT/IDCT using direct method

TLDR
This work develops a novel 8/spl times/8 two-dimensional (2-D) discrete cosine transform/inverse discrete Cosine transform (DCT/IDCT) architecture based on the direct 2-D approach and the rotation technique.

A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs

TLDR
This paper presents a design of a fast 2D-DCT hardware accelerator for a FPGA-based SoC and shows that this architecture provides optimal performance/area ratio with respect to several alternative designs.

An efficient 2-D DCT/IDCT core design using cyclic convolution and adder-based realization

TLDR
It provides a design-automation environment with parameter configurations in designing a 2-D DCT/IDCT core that is suitable for most image and video compression applications and can save on average 20% in the delay-area product.

A new time distributed DCT architecture for MPEG-4 hardware reference model

TLDR
The proposed TDA optimizes the two-dimensional discrete cosine transform (2-D-DCT) architecture performance by using a time distribution mechanism to exploit the computational redundancy within the inner product computation module.

Architecture Design of Shape-Adaptive Discrete Cosine Transform and Its Inverse for MPEG-4 Video Coding

TLDR
This paper presents efficient VLSI architectures of the shape-adaptive discrete cosine transform and its inverse transform for MPEG-4 and exploits the numerical properties found in the transform matrices of various lengths to derive a fine-grained zero-skipping scheme for the SA-IDCT.

A high-speed 2-D transform architecture with unique kernel for multi-standard video applications

TLDR
Owing to the proposed unique kernel framework, the adder matrices, which only have 13 adders, are independent to the coefficients of the 2-D transform and can be easily realized via proposed uniquekernel and the efficient routing network to accomplish multi-standard video coding requirement.

A 100 MHz 2-D 8×8 DCT/IDCT processor for HDTV applications

TLDR
The design of a combined DCT/IDCT CMOS integrated circuit for real time processing of HDTV signals and critical path simulation indicates a maximum input sample rate of 100 MHz.

A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization

This work describes the implementation of a discrete cosine transform (DCT) core compression system targetted to low-power video (MPEG2 MP@ML) and still-image (JPEG) applications. It exhibits two

Fast algorithms for the discrete cosine transform

TLDR
Algorithms for computing scaled DCTs and their inverses have applications in compression of continuous tone image data, where the DCT is generally followed by scaling and quantization.