SMT-based verification of parameterized systems

@inproceedings{Gurfinkel2016SMTbasedVO,
  title={SMT-based verification of parameterized systems},
  author={Arie Gurfinkel and Sharon Shoham and Yuri Meshman},
  booktitle={SIGSOFT FSE},
  year={2016}
}
It is well known that verification of safety properties of sequential programs is reducible to satisfiability modulo theory of a first-order logic formula, called a verification condition (VC). The reduction is used both in deductive and automated verification, the difference is only in whether the user or the solver provides candidates for inductive invariants. In this paper, we extend the reduction to parameterized systems consisting of arbitrary many copies of a user-specified process, and… CONTINUE READING