SMT-Directory: Efficient Load-Load Ordering for SMT


Memory models like SC, TSO, and PC enforce load-load ordering, requiring that loads from any thread appear to occur in program order to all other threads. Out-of-order execution can violate load-load ordering. Multi-processors with out-of-order cores detect load-load ordering violations by snooping an age-ordered load queue on cache invalidations or… (More)
DOI: 10.1109/L-CA.2010.8


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