SLID-ICV Vertical Integration Technology for the ATLAS Pixel Upgrades

@article{Macchiolo2012SLIDICVVI,
  title={SLID-ICV Vertical Integration Technology for the ATLAS Pixel Upgrades},
  author={Anna Macchiolo and Ladislav Andricek and H-G. Moser and Richard Nisius and Rainer Helmut Richter and Philipp Weigell},
  journal={Physics Procedia},
  year={2012},
  volume={37},
  pages={1009-1015}
}
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Production and characterisation of SLID interconnected n-in-p pixel modules with 75 μm thin silicon sensors
SLID Interconnected n-in-p Pixel Modules with 75 Micrometer Thin Silicon Sensors
The performance of pixel modules built from 75 micrometer thin silicon sensors and ATLAS read-out chips employing the Solid Liquid InterDiffusion (SLID) interconnection technology is presented. This…
Production and Characterisation of SLID Interconnected n-in-p Pixel Modules with 75 Micrometer Thin Silicon Sensors
Thin n-in-p pixel sensors and the SLID-ICV vertical integration technology for the ATLAS upgrade at the HL-LHC
Development of pixel detectors for particle physics using SLID-ICV interconnection technology
  • H. Moser, L. Andricek, P. Weigell
  • Physics
    2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International
  • 2012
TLDR
Using the SLID-ICV technology from Fraunhofer EMFT, thin pixel sensors with 50μm × 400μm pixel size are connected to the readout ASICs (ATLAS FE-I3) and complemented with vias.

References

SHOWING 1-10 OF 11 REFERENCES
Performance of thin pixel sensors irradiated up to a fluence of 1016neqcm−2 and development of a new interconnection technology for the upgrade of the ATLAS pixel system
Development of thin pixel sensors and a novel interconnection technology for the SLHC
Development of a versatile and modular test system for ATLAS hybrid pixel detectors
Performance of n-in-p pixel detectors irradiated at fluences up to 5x10**15 neq/cm**2 for the future ATLAS upgrades
3D-integration of silicon devices: A key technology for sophisticated products
  • A. Klumpp, P. Ramm, R. Wieland
  • Engineering, Materials Science
    2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
  • 2010
TLDR
All these 3D integration concepts focus on wafer level processing to achieve the highest miniaturization degree and highest processing reliability as well as enabling high volume cost-effective fabrication.
Development of thin sensors and a novel interconnection technology for the upgrade of the ATLAS pixel system
3D System Integration Technologies
  • E. Beyne
  • Computer Science
    2006 International Symposium on VLSI Technology, Systems, and Applications
  • 2006
TLDR
This paper defines the key technologies for realizing true 3D interconnect schemes as respectively 3D-SIP,3D-WLP and 3d-SIC, which can be categorized as a more traditional packaging approach, a wafer-level-packaging, WLP approach and a foundry level ('below' passivation) approach.
Processing of ultra thin silicon sensors for future e/sup +/e/sup -/ linear collider experiments
The e/sup +/e/sup -/ linear collider physics program sets highly demanding requirements on the accurate determination of charged particle trajectories close to the interaction point. A new generation…
Perfomance of thin pixel sensors irradiated up to 1016 neq/cm2 and development of a new interconnection technology for the upgrade of the ATLAS pixel system
  • NIM A,
  • 2011
Processing of ultra-thin silicon sensors for future e+e- linear collider experiments
  • IEEE Trans. Nucl. Sci
  • 2004
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