SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration

Abstract

A 10-b, 100-MS/s pipelined analog-to-digital converter (ADC) without dedicated front-end sample-and-hold amplifier (SHA) converts from dc to the 12th Nyquist band with in situ, mostly digital background calibration for the clock skew in the 3.5-b front-end stage. The skew information is extracted from the first-stage residue output with two comparators… (More)
DOI: 10.1109/JSSC.2011.2151510

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Cite this paper

@article{Huang2011SHALessPA, title={SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration}, author={Pingli Huang and Szukang Hsien and Victor Lu and Peiyuan Wan and Seung-Chul Lee and Wenbo Liu and Bo-Wei Chen and Yung-Pin Lee and Wen-Tsao Chen and Tzu-Yi Yang and Gin-Kou Ma and Yun Chiu}, journal={IEEE Journal of Solid-State Circuits}, year={2011}, volume={46}, pages={1893-1903} }