SET Emulation Under a Quantized Delay Model


Single event transient (SET) fault analysis is usually performed trough digital simulation at the gate level. However, this method cannot be used for large fault injection campaigns, since gate level simulation is quite slow. In this paper, we propose an approach to build an FPGA based SET emulator, which implements a quantized delay model of the circuit… (More)
DOI: 10.1007/s10836-008-5081-3


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Citations per Year

Citation Velocity: 14

Averaging 14 citations per year over the last 3 years.

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