SAT for heterogeneous FPGA technology mapping

@article{Fan2011SATFH,
  title={SAT for heterogeneous FPGA technology mapping},
  author={Quanrun Fan and Sun Jian-yong},
  journal={2011 International Conference on Electric Information and Control Engineering},
  year={2011},
  pages={4449-4452}
}
Modern FPGAs employ heterogeneous architecture to reduce power dissipation, area overhead, and to improve performance. Besides lookup tables, heterogeneous FPGA also contains ASIC-like sub-circuits and macro-gates. If a programmable logic block with n inputs contains macro-gates, a Boolean function with n variable may not be implemented in it. In this paper, a Boolean satisfiability based technology mapping methods is suggested, which us symmetry to speed up the mapping process. 

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