SAT-Based Combinational Equivalence Checking with Don’t Care

Abstract

In recent years, many approaches have been investigated for combinational equivalence checking problem. Despite the huge size of works, there is no work for combinational equivalence checking dealing with don’t care. In this paper, we propose a method for combinational equivalence checking with don’t cares. In particular, our technique proves the logical-consistency of circuits containing don’t cares. In checking equivalence, we use SAT for equivalence checking problem instead of using BDDs or simulation. In verification, there can be false negatives which come from don’t care space. False negatives can be eliminated using ternary simulation and model accumulation. Keywords—Equivalence Checking, Don’t Care, Satisfiability

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Cite this paper

@inproceedings{Nam2004SATBasedCE, title={SAT-Based Combinational Equivalence Checking with Don’t Care}, author={Myoung-Jin Nam and Chang-Hun Sung and Jin-Young Choi}, year={2004} }